1. Field of the Invention
The present invention relates to a method for testing a plurality of devices, and in particular, to a method for testing a plurality of devices arranged on a wafer such that yield losses during electrical tests on a wafer level are strongly minimized.
2. Description of the Related Art
FIG. 1 shows an example of a wafer 100, on which a multitude of devices or chips 102 is formed, wherein, in FIG. 1, only examples of individual ones of the devices 102, which are suggested by the squares, are provided with this reference number to maintain the clarity of the drawing. The individual devices/chips 102 each include inputs and outputs as well as supply terminals, which, as long as the devices/chips 102 have not been diced, are connected via a common contact element (e.g. a probe card, PCE, etc.) or also on the wafer, resulting in common data lines for input and output signals.
Further, supply lines (ground, supply voltage, etc.) are provided for the devices/chips 102, for example in the contact element or on the wafer (not shown in FIG. 1). In accordance with an example, each of the devices/chips 102 is assigned as supply line. Alternatively, several devices/chips 102 on the wafer are connected to a common supply line such that a region on the wafer will be supplied by a supply line. The supply lines provide the devices/chips 102 located on the wafer with the potentials required for their operation, wherein the term supply line refers to both a voltage-conducting line and a ground line. This enables to simultaneously test a plurality of devices/chips, as will be explained in more detail below.
The testing means, as it is eg known from conventional wafer tests, divides the wafer 100, depending on the number of the available input/output channels of a test unit, into a predetermined number of areas, as an example in FIG. 1, into four areas I, II, III, IV, which, in FIG. 1, for example, each include a predetermined number of devices/chips 102 in three columns. The test unit, which is not illustrated in more detail, further includes one or more data buses 104, in the example with a first data line 104a, a second data line 104b and a third data line 104c, serving to receive data signals from the individual columns on the wafer 100 or to provide them to the same.
In area I, the devices/chips of the first column are connected to the third data line 104c. The devices/chips in the second column are connected to the first data line 104a. In the remaining areas II to IV, the devices/chips in the first column are connected to the second data line 104b, the devices/chips in the second column to the third data line 104c, and the devices/chips in the third column are connected to the first data line 104a. 
In the embodiment shown in FIG. 1, eleven consecutive rows, as suggested by the eleven horizontal arrows 106, are measured, wherein, however, the testers used comprise only four input/output channels such that, in each row, a maximum of four devices/chips 102 may be simultaneously measured/tested. Alternatively, more input/output channels may be provided, with which more devices/chips 102 may be simultaneously measured/tested. The selection of the devices/chips to be measured will be effected via applying a selection signal (CHIP_SELECT) to the corresponding row (arrows 106) and by activating selected data lines. FIG. 1 shows an example of the state, when already five rows have been passed, such that the selection signal is now only to be provided to the row 107. By applying the selection signal to the row 107 and by activating the data line 104a of the data bus 104, the device 108 in the second column in the area I and the devices 110, 112, 114 in the third column of the areas II to IV are selected for a test. Analogously, the activation of the data line 104b would cause the devices in the first column of the areas II to IV to be selected, and the activation of the data line 104c would cause the devices in the first column of the area I as well as in the second columns of the areas II to IV to be selected.
In order to be able to simultaneously measure as many chips as possible on a wafer, more or less devices/chips 102, depending on the number of available channels of the tester, are integrated in groups, as described above.
A disadvantage of the above-described procedure becomes manifest when one of the chips 102 to be tested is defective. In FIG. 1, examples of the four single chips 108, 110, 112 and 114 are illustrated, which are examined in a row, when a selection signal is applied. Now assume that the device/chip 112 is defective, as is made clear by the sign “X”. The error of the device may refer to fabrication-related errors resulting in short-circuits to ground or to an operating voltage within the device 112,. The disadvantage in the above-described procedure is that, on the basis of these short-circuits, the inputs or outputs of the other directly connected chips 108, 110, 114 are also tied to the corresponding potential, and it is thus impossible to conduct convincing measurements. Thus, all devices/chips 108, 110, 112, 114 connected in this measurement will be lost, since their functionality may not be tested, and these devices will be completely rejected as erroneous, which clearly reduces the yield.
FIG. 2 schematically illustrates once more the examination of the devices 108 to 114. A tester 106 is schematically shown, which applies the input signals required for the tests to the devices 108 to 114 across the resistor R and which receives output signals from these devices 108 to 114 and forwards them to an assessment means to examine and classify the functionality of the tested devices 108 to 114. In the illustrated embodiment, the tester 116 has a functionality, which enables the same to handle for channels (I/O-channels) at a time, i. e. to simultaneously provide four devices with signals and to receive output signals from the same.
FIG. 2 schematically shows a common data line 118, which is formed in the contact element or on the wafer, with which the individual devices 108 to 114 are connected on the wafer via data lines 108a to 114a. The tester 116 is connected eg via the contact element or directly to the wafer 100, and, in this case, to the common data line 118, to perform the corresponding measurements. The data line 118, which is schematically illustrated in FIG. 4, is for example the activated common data line 104a of the data bus 104, which is shown in FIG. 1. If, on the basis of a defect in the device 112, the data line 112a of the same is grounded or is at another operating potential, the remaining devices 108, 110, 114 are also brought to this potential on the basis of this connection. Therefore, a convincing measurement is no longer possible, and the reduction in yield already been mentioned above, which is due to the missing determinability of the functionality of the devices 108 to 114, is caused.
To avoid these problems, certain electrical tests of the devices/chips 102 were not carried out on a wafer level so far. Instead, the individual devices were first diced, and then the corresponding test was carried out on a device level. Storage elements, which are eg equipped with laser fuses, were also not submitted to the related burn-in process on the wafer level, but, as well, first on the device level. This way, the prior art ensured that, in a test, only known, functioning devices/chips were used such that practically no yield loss exists, since, on the one hand, building blocks with internal short-circuits do only seldomly occur, and, on the one hand, they may be exchanged after a preliminary test. However, this is only possible, since the building blocks have already been diced; but this is not possible on the wafer level.
A further possibility of solving the problem on the wafer level is to mask defective devices/chips, which, however, is only possible by covering the contacts or the entire device with an insulating layer. Applying the insulating layer in this way, however, represents an additional and cost-intensive step, which stands in no relation to the enhanced yield, and which, therefore, should be avoided, if possible.
Based on this state of the art, the present invention is based on the objective of providing a method for testing devices on a wafer level, which reduces the yield losses in such electrical tests on wafer level.